CISC vs RISC¶
About Processor Instruction Sets¶
Learning Objectives: Characteristics of RISC and CISC instruction set architectures and their comparison.
Since the 1980s, there have been two major approaches to processor instruction sets, along with their implementations and microarchitectures. We will briefly discuss these approaches below.
CISC¶
CISC (Complex Instruction Set Computer) architectures aim for a broad machine language instruction set with versatile instructions. Historically, the idea was to make machine instructions resemble high-level programming language instructions, providing direct hardware support for them.
This allows programs to achieve efficiency by performing complex operations in a single instruction, such as generating an encryption key. Another advantage is that fewer machine instructions are needed to implement a program. For example, CISC instructions can operate directly on memory without requiring data to be first loaded into registers.
Thus, CISC complicates microarchitecture, and CISC instructions are typically implemented as microprograms that run internally within the pipeline (multiple cycle/pass computer). The diagram below shows the principle where, starting from the Decode phase of the pipeline, a microprogram instruction is executed, and its results are fed into the Execute phase as operands for the ALU.
Microprograms can be implemented either using the processor’s machine language or hardware description languages.
Characteristics of CISC instruction set architectures:
- Instructions for both simple and complex operations.
- The operation code specifies whether the instruction is a microprogram.
- As a result, instruction length (in bytes) varies greatly.
- Multiple addressing modes.
- Instructions can perform direct memory addressing.
- An instruction can operate on entire memory regions rather than just a single memory address.
- Instruction execution time varies significantly.
- Execution time can span hundreds of clock cycles...
Disadvantages of CISC include the complexity of processor microarchitecture implementations. Also, microprograms may require pipeline phases to loop multiple times, effectively within a single machine instruction, leading to longer execution times. Additionally (especially in earlier times), high-level language compilers did not always effectively utilize CISC instructions.
Implementations¶
Modern PC processors are largely based on Intel's CISC instruction set architecture. For example, in the x86 processor family, new CISC-based instructions have been added with each generation. Today, the full documentation for Intel's instruction set spans thousands of pages across three parts.
An example from the x86 CISC instruction set, where two instructions, repne (repeat if not equal) and scasb, are used to search for a character in a string:
# Find the position of the character 'e' in the string my_string mov ecx,my_string_len mov edi,my_string mov al,'e' cld repne scasb
Example: From Motorola's 68000 processor CISC instruction set, a single transfer instruction can move data from multiple registers and simultaneously perform an arithmetic operation:
# Move a word (w) from the memory location pointed by register a0 # to the memory location pointed by register a1, incrementing both registers by a word size move.w (a0)+,(a1)+ # Move 32-bit registers (l) d0, d4-d7, and a2-a6 to the stack, # but first adjust the stack pointer (sp) movem.l d0/d4-d7/a2-a6,-(sp)
RISC¶
RISC (Reduced Instruction Set Computer) instruction sets focus on maximizing processor efficiency through simple (and therefore fast) machine language instructions. This leads to simpler implementations, control logic, and microarchitecture. In RISC architecture, an instruction is executed in a single pipeline pass (single cycle/pass computer).
The motivation behind RISC development was the observation that CISC instructions did not always deliver optimal performance. Instead, breaking instructions into smaller parts could speed up execution and/or improve overall performance (IPS), as implementing pipelining for CISC instructions is challenging.
Characteristics of RISC architectures:
- The instruction set consists of simple instructions performing small operations.
- High throughput with pipelining.
- Flexible machine code programming as functionalities can be implemented in various ways.
- Program code optimization is more challenging and often falls to the compiler.
- Instructions have a fixed length across all instructions.
- May include memory addresses as immediate values.
- Operands are mainly registers.
- Fast execution since operations are mostly register-to-register.
- Memory addressing is restricted to dedicated load/store instructions.
- Enables constant execution times.
- Minimizes (slow, >1 clock cycle) memory accesses.
- Numerous registers are used to bring more data closer to the processor.
- For instance, the AVR architecture (e.g., 8-bit Arduinos) has 32 general-purpose registers.
- Data hazards are expensive!
- Limited addressing modes.
- Emphasis on immediate addressing to minimize address decoding logic.
Implementations¶
RISC architectures are favored in embedded systems and digital signal processors (DSP). For example, the well-known AVR architecture by ATmel is clearly RISC. Refer back to the assembly loop code presented earlier in the introduction. Can you identify RISC traits in the code?
In modern PC systems, CISC instruction sets are actually translated into RISC instructions by an internal secondary decoder (e.g., AMD's K5 processor). It has been estimated that implementing one x86-CISC instruction requires 3–4 RISC instructions. As a result, executing simpler RISC instructions is easier to pipeline, thereby improving throughput.
Intel Pentium processors from a couple of decades ago are RISC-based (3 million transistors). As shown in the earlier material, Pentiums have two pipelined integer units (actually based on the previous 80486 model) and an 8-stage pipelined floating-point unit. The control unit includes instruction pairing logic to execute two instructions simultaneously. Pentiums translate (CISC) instructions into RISC micro-operations.
Example: The aforementioned 68000 processor instructions could easily be translated into RISC instructions.
Example: The RISC-V open RISC instruction set architecture was developed at the University of California, Berkeley, in 2010. It is freely available for anyone to use in their processor designs. For example, RISC-V implementations are being developed or already exist for big data analytics and graphics processors.
CISC vs RISC¶
The table below summarizes the differences between CISC and RISC architectures.
CISC | RISC |
Many complex instructions | Few simple operations per instruction (typically fewer than 100) |
Instructions with variable (long) execution times | Instructions with short, fixed execution times |
Instruction length varies from 1–15 bytes (x86) | Instruction length is the same across all instructions (typically 2–4 bytes) |
Many addressing modes for memory and operands (e.g., displacement, indexing) | Simple direct addressing modes with many registers |
ALU operations directly on registers and memory | ALU operations only on registers, with separate load/store instructions for memory |
Instructions automatically set processor status flags | No (or fewer) status flags; results are visible in general-purpose registers |
Extensive use of the stack for arguments and memory addresses | Arguments and memory addresses stored in registers, minimizing memory usage |
Processor implementation details hidden from the programmer | Implementation constraints are reflected in machine code, limiting what and how to implement |
Additional bibliography¶
Please refer to the course book Bryant & O'Hallaron, Computer Systems: A Programmer's Perspective, 3rd edition. Chapter 4.
Conclusion¶
Modern processor architectures have adopted the best features from both models, and we will revisit this topic in later material.
The authors of one of the course's textbooks, David Patterson and John Hennessy, were actually the first to propose and develop the RISC architecture model in the 1970s and 1980s.
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